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PCB layout rules
Text marking for silkscreen layer
PCB Fiducial Mark design
PCB fixed position hole
SMT component PAD design
PTH component PAD design
Through-hole(Via)design
Trace design
other limitation
PCB layout rules
V-Cut layout rules :
Chips to V-Cut line should be more than 1mm, otherwise will damage chips or will change to use Stamp Cut design , will add the PCB cost.
The distance to PCB edge 0.5mm, can not layout the trace, The distance to PCB edge 1.0mm,can not layout the any component.
The distance to PCB edge 5mm, can not layout the components height over 25mm, otherwise cuter will damage components.
PCB trace to V-Cut should be more then S=0.5mm safety buffer, otherwise will have the risk to damage the trace.
When we use V-Cut
PCB thickness 1.0mm to 3mm(1.0mm to 0.5mm + SMT pallet).
PCB outline is square type or rectangle type, irregular shape can not use the V-Cut.
Stamp design :
Stamp design only for irregular PCB, PCB to PCB layout distance is 2mm, V-Cut only 0.3mm.
Stamp design parameters .
V-Cut VS Stamp layout :
PCS to PCS distance only 0.3mm for V-Cut, we can save the PCB layout cost.
Stamp Cut design, PCB PCS to PCS distance is 2mm.
Base on same PCS design with different Cut type( stamp/V –Cut), the PCB cost will impact 10- 25%.
V-Cut PCB will be cut by machine, but Stamp Cut will broken by OP and have stress then damage the components.
PCB/panel layout
Why don’t choose single PCB for SMT process :
We need to put the each single PCB on carrier when do SMT process
But carrier cave and single PCB have tolerance , so always happen solder paste printing misalignment then will get the shift/tombstone process issue
Sometimes will happen single PCB lift up from SMT carrier and will have the chips mounting shift/missing process issues
Factors of impact PCB Cost
PCB layout
Fine pitch components
Panel V-Cut/Stamp Cut/PCB conveyor edge size
PCB drill hole size/quantity
PCB material cost
PCB process easy/complicated , process spec
PCB surface finished process also impact cost, OSP/IMS/EING/IMT
PCB outline, regular shape is cheaper than irregular shape ,
Text marking for silk layer
The current situation:
We received the gerber file for UK design team ,no silk layer be found .
We can not directly confirm Polarity of component on the PCB , can not confirm the location of component ,easily to confirm IC shift or not .
In the production adjustment X, Y coordinate and confirmation the location completely rely on engineering drawings ,Big waste of time.
Component outline& polarity marking design definition:
Text marking, keep away from Via Hole or Through Hole as far as possible .
Text marking , Silk screen printing character, polarity and polarity signs can not components be covered .
Text height≥25 mil ,line width ≥5 mil
Beside the BGA/CSP ,component outline should not smaller than actual component size.
The text does not overlap
SMD/PTH component text marking include body outline , pin assignment ,component name ,polarity marking .as below:
Component outline& polarity marking
Tantalum capacitor or diode ﹝3 PIN﹞
SOP/SSOP
QFP
QFN
BGA, CSP marking
PCB number and version
(i) PCB Model
(ii) PCB Part number and version
(iii) text height : 80mil
PCB 板号说明如下：公元年度后两码 ( 06 , 07 )
全新 PCB 必需附予板号及 -SA (Sample A) 版本，尔后修改版本依序为 -SB、-SC，或 -1A 、-1B 、-1C ...等，量产时版本必需为 -1、-2、-3等
PCB Fiducial Mark design
The current situation: Many projects did not design fiducial mark-in, the machine can not recognize to position, cause no high precision print/mounted
Three fiducial mark-out located diagonally on board, and do follow related dimension requirement . fiducial mark dimension is 1mm(d) and solder mask is 3mm(D) . The diagonal fiducial mark should not be symmetrical, it should be keep away at 5 mm.
Fiducial PAD edge keep 4mm distance from the edge of PCB
Single board must have two fiducial mark –in located diagonally on the board.
PCB fixed position hole
Tooling holes on all boards are called out with correct dimensions, tolerances, and are non-plated. ( 3.55mm +0.075/-0 or 2.18mm +0.05/-0.05)
There should be 3.81 mm arc located at 4 corners of PCB to avoid stuck at conveyor and damage of packing material.
SMT component PAD design
NG symptom: 0402 chip tombstone
For example: D500+ FN700054 chip 0402 chip tombstone defect rate:1.0%
NG picture:
Analysis: PAD to PAD space is too big caused the tombstone after IR .
Non specifications within RLC Pad design according to the following principles
(i) B= max of W1, to prevent the shift
(ii) C=10 + H(electrode width) + 15 mil
(iv) restricted area L2: A+10mil ,W2=max: (" W1 + 8 + max of tolerance" , " B + 10 ")
(1) Resistance and inductance components size list
(2) capacitance component size list
Note: besides the chip 0201/0402,the rest is for reference only
(3) STC3216~7343
Note : No chips component that size below 0603 located beside 7347 and 6032 tantalum capacitor within 2.6mm pad to pad distance. If un-avoidable, the chip components should be vertical with the tantalum capacitor.
(4)Electrolysis capacitor parts size list
(5)Diode-3PIN
(8)IC types
a. SSOP, SOP
b.QFP
(9)QFN
(10)BGA, CSP
PTH component PAD design
In order to simplify and improve the printing circuit welding (soldering) process , The special development of through-hole reflow technology (Pin-in-Paste) The through-hole type connector from Dipping process ,change to SMT printing solder paste and reflow replaced . Place all thru-hole parts on topside of the board. (Avoid manual soldering process)
B : aperture size≧pin diameter size +0.25 mm ( 10 mil )
A : The outer layer of the minimum pad size ≧ aperture size+ 0.36 mm (14 mil )
According to the manual soldering parts : Pad size (ΦA) = Hole size (ΦB) + 40 mil
PTH design guideline
Parts of pin diameter and through the aperture ratio (PH) principle:
Pin to hole rate (ØP / ØH) should fall within 0.6~0.8, shown as diagram:
PH= 0.6~0.8 the best ; PH= 0.4~0.5 Acceptable ; PH < 0.3 not acceptable
If any annular ring of PTH connect with connector or PTH pad, please add solder mask to isolate each other (width 20mil at least).
As PSU A000116 Design issue, between PAD with Ground no solder mask covered cause the solder bridge /empty solder.
The distance between the PTH and chips too is very close when manual solder has the risk for broken and solder short . besides arrange Ops to manual solder ,no choice, Waste a lot of manpower and delay output.
PTH restricted zone:
For pin in paste process, keep at least 3mm distance between edge of hole ring and pad.
Through-hole(Via)design
Via hole under the component body
Via hole under the smt component body ,need to confirm this PCB whether through wave soldering process ,if so, need to blind and buried via hole. Otherwise, there will be the risk of overflow from the hole of Via solder.
(1) The normal PAD layout (Within the PAD pins )
‧ Inner band area (10mil) Via Hole can not be placed.
‧ outline band area(10mil) ,Via Hole can not be placed.
(2) Un-normal PAD layout ( the pin of the component over the PAD )
‧inner band area (A + 10mil ) Via Hole can not be placed
‧outline band area (10mil ) Via Hole can not be placed
Trace design
Power Trace to strengthen
PAD/Via hole with Trace to junction need to strengthen，the general way (Power Trace，the rest of type refer to Tear drop design)
Add tear drop
In the outer trace add tear drop as below icon:
(1) When the line width is less than 8 mil ,In pad and trace junction with width of 8 mil and length of 6 mil trace .
(2) When the line width is more than 8min,do not add Tear Drop
(3) If the distance is not enough to add a Tear Drop, can be ignored.
Trace lead the way
Trace line and the hole,be recommended in the following.
Other limitation
Component placement limitation
Board edge parts restriction (including the process edge size)
(i) In SMT stage, there should be no any component body or pad within 4 mm along pcb edge that used for conveyor transfer.(as below the upper and the lower sides), Within 2 mm from pcb edge that vertical to the conveyor. PIP or PTH component body should not out of pcb edge.
Board edge parts restriction (including the process edge size)
(ii) In SMT stage, the component height should lower than 2 mm when it away from pcb edge 4~6mm ( indicated in pink color region).
Deformation limit
B/A≤7.5/1000, and the maximum deformation of B must be less than 1.2 mm
PCB thickness limit: 1 ~ 1.6 ± 0.127 mm or 10%
PCB substance selection
The pcb prepreg should meet criteria of Tg ≧145℃.
The pcb prepreg should meet criteria of Td>320 ℃.
PIP parts limit
All of the through hole part must be designed in second to avoid the use of hand soldering process The first surface is necessary to use the SMD TYPE part or through hole parts pin and parts body can not outstand PCB second surface
The spec of pin out of pcb surface in PIP process :
pin length ≒ PCB thickness + 0.3~0.6 mm
The insert parts in PCB can not tilt, dumping or easy to loose state.
Choose the component :The use of chip components in the SMT stage as far as possible, reduce the waste of human action.
No trace cutting or jump wires process on mass production models.
PCB pad size should be match with the size of components , If the same parts have different appearance size ,the Layout or according to process proposals to special Layout, must conform the rule。All of pad design need to non-solder mask design.
Passive component pad size
The general RLC component：place outline area do not overlap
Gerber file layers requirement
SMD layer: component PAD , reference this layer to design stencil aperture
Silk layer: SMD component text marking include body outline , pin assignment ,component name ,polarity marking
Solder mask layer
Place layer :check the component location
Drill layer :confirm the through-hole size whether it match with the component
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