/ TOPCon 结构隧穿氧化层中 pinhole 密度钝化影响 /

• 来源：Will SiOx-pinholes for SiOx/poly-Si passivating contact enhance the passivation quality?
• DOI：https://doi.org/10.1016/j.solmat.2023.112200
• 关键词：TOPCon，隧穿氧化层，pinhole密度，钝化性能

关键结论

• 适量的pinhole密度可以增强钝化效果。钝化的增强源于通过pinholes增加的杂质源扩散增强了场钝化效果，但过量的pinholes时，掺杂源扩入过多，俄歇复合加剧，钝化效果反而变差。
• 对于热氧化SiOx（LPCVD），pinholes密度在量级，对于PAOS-SiOx适用范围需要自行探索。SiOx成膜方式影响隧穿层致密性，对应退火高温过程pinhole密度不同。
• pinholes密度随退火温度呈指数级变化，温度过高，pinholes密度太大，掺杂源通过pinholes大量进入c-Si（ECV曲线表现为穿透SiOx特征），俄歇复合加剧，钝化会变差。

实验方案

两步退火处理研究氧化层中pinholes影响

• 预退火，用于形成pinholes
• 后退火，离子注入方式掺杂，通过后退火将掺杂元素的激活

双面对称结构

• SiOx制备，<111>晶向硅片，热氧化法，675℃ Tempress 炉管，1.4±0.1 nm （J.A. Woollam椭偏仪量测）
• poly-Si制备：LPCVD，580℃，膜厚100±5 nm
• 掺杂：离子注入方式掺杂P（或B），注入参数：
• 能量 20 keV（5 keV）
• 掺杂量 ()
• 退火处理：Tempress机台
• pinhole量测组别：退火温度1000-1075 ℃，1min用于产生pinholes，升降温速率 10℃/min。之后5% TMAH溶液刻蚀 70℃，180s。量测pinholes密度
• 钝化验证组别：n-FZ硅片，样品离子注入前同pinhole量测组别，离子注入后，后退火处理激活掺杂元素。H化处理方式PECVD SiNx capping层，FGA 400℃退火30min。
• 后退火温度低于前退火温度，后退火产生的pinholes相比前退火有数量级差异，可以忽略不计。
• 量仪：J.A. Woollam椭偏仪、ECV、WCT120、TCAD Sentaurus模拟分析软件

结果讨论

热预算 TB，thermal budget，对掺杂曲线尾态分布doping tail有影响

pinholes密度与退火温度影响

• 1000-1075℃退火温度范围内，相同退火时长，温度越高，pinholes密度越高（数量级差异）

Optical microscope top view images of etched-back poly-Si samples prepared with pre-annealing for 1 min at temperature of (a1) 1000 ◦C, (a2) 1025 ◦C, (a3)1050 ◦C, and (a4) 1075 ◦C, according to which the calculated pinhole density as a function of the pre-annealing temperature is plotted in (b). The averaged pinhole density values are obtained from 3 samples manufactured per each pre-annealing temperature.

【热扩散预算TB】Thermal diffusion budget

• 离子注入后，后退火处理过程，poly-Si中掺杂原子P或B激活并向SiOx→c-Si硅体内扩散，扩散进入c-Si中的掺杂元素直接影响掺杂曲线的尾态分布及场钝化效果
• 半导体中“热扩散预算”用于表征扩散掺杂对照，引入TB概念，指导后退火处理过程所需退火温度
• - 离子注入后退火时长
• - 扩散系数（c-Si中扩散系数P - ，B - ）
• - 激活能 (P - 2.74 eV，B - 3.12 eV)
• B的热预算TB要比P高2倍以上
• P或B在SiO2中的扩散系数在量级，比在Si中高的多，可不用考虑掺杂源在氧化层中扩散影响

钝化效果 vs TB

• 双面对称结构 钝化结构，经H化处理FGA退火处理，钝化结果
• TB处理有个最佳区间，过小或者过大钝化效果均会下降
• pinholes密度在一定范围内可提升钝化性能
• 对于钝化效果，pinholes密度和TB有个最佳工艺窗口

Fig. 4. The passivation quality diagram maps the pinhole density on the preannealing temperature (for 1 min annealing) and the TB on the post annealing temperature/time settings versus the iVOC of the passivation quality evaluation samples. The pinhole density values were characterized from the flat wafers, while the calculated TB values for n+ poly-Si samples were prepared on double side textured c-Si wafers. The reported iVOC values were measured after the hydrogenation step without removing the SiNx capping layer. STB and Spinhole are two series of samples in which we varied TB for a fixed pinhole density or pinholes density for a fixed TB, respectively. The colored stars overlaid on the diagram indicate the samples used for studying ECV profiles in Figs. 5 and 7.

Fig. 5. The ECV doping profile (a) and the calculated electric field profile (b) of the post-annealing TB series (STB) samples. Corresponding i-Voc values extracted from lifetime curves measurements in (c) are inserted in (a).

后退火处理温度850 vs 875 vs 1000℃条件，钝化结果对比：

• 875组别P掺杂曲线与850组别基本相当，但iVoc高7mV。对应c-Si中P扩散浓度略高，场钝化优于850组别（高低浓度结-场钝化）
• 1000℃组别钝化效果最差，P扩入c-Si过多，俄歇复合加剧，钝化变差

Fig. 6. Sketches for the electrical field, E, at the interfaces of poly-Si/t-SiOx/c-Si for the thermal budget series (STB) (a1 = low TB, a2 = medium TB, a3 = high TB) and for the pinhole density series (Spinhole) (b1 = no pinholes, b2 = low pinholes density, D1x, b3 = high pinholes density, D10x).

钝化效果 vs pinhole密度

• 对比不同前退火（pinhole密度不同），相同后退火处理（875℃，30min）组别钝化效果
• 无pinhole组，iVoc最低；pinhole适中组别钝化效果最好（727 mV）；pinhole密度过大钝化效果变差
• 表明，适量的pinhole密度可以增强钝化效果。钝化的增强源于通过pinholes增加的杂质源扩散增强了场钝化效果，但过量的pinholes时，掺杂源扩入过多，俄歇复合加剧，钝化效果反而变差。

Fig. 7. The ECV doping profile (with iVOC in the inset) (a) with calculated electric field profile (b) and (c) the lifetime curves for the pinhole density (pre-annealing) series (Spinhole) samples. The curves in the dashed box in (b) are zoomed in (d).

对于p+ poly-Si情况，上述结论仍适用

Fig. 8. (a) Passivation quality diagram maps the pinhole density on the pre-annealing temperature (for 1 min annealing) and the TB on the post-annealing temperature/time settings versus the iVOC of the evaluation samples. The pinhole density values were characterized from the flat wafers, while the calculated TB values for p + poly-Si samples were prepared on double side textured c-Si wafers. The reported iVOC values were measured after the hydrogenation step without removing the SiNx capping layer. STB and Spinhole are two series of samples in which we varied TB for a fixed pinhole density or pinholes density for a fixed TB, respectively. The colored stars overlaid on the diagram indicate the samples used for studying ECV profiles. The ECV doping profile (with iVOC in the inset) and the calculated electric field profiles of the STB and Spinhole series samples are reported in (b and d) and (c and e), respectively.