AMD interview Questions (Physical Design)
科技
2024-10-31 12:20
中国香港
- Tell me about your experience.
- How will you make sure that your power structure is good?
- Tell me about DRC and LVS fixes.
- Why we are following certain guidelines for macros placement and what are those guidelines?
- What is the minimum space required in between macros if the channel is there on the non-pin side of macros?
- What is the distance between tap cells in your design?
- What are the setup and hold edges for a 3-level multi-cycle path?
- What are the setup and hold edges for the half-cycle path?
- How you will perform cell spreading in placement if congestion is there?
- Tell me about the 2-pass approach in placement.
- Why we are not taking care of hold violations at the placement stage?
- Tell me about multi-source CTS.
- Tell me about Switching power, internal power, average power, peak power, and IR Drop.
- Tell me about CPPR.
- What are the differences between OCV and POCV?
- What are the setup and hold edges for the half-cycle path?
- What are the setup and hold edges for the positive latch to negative flop?
- Tell me about setup and hold violation fixes which are occurred in the same path.`
- How will you apply to derate?
- Tell me about DPT.
- Tell me about X-talk delta and X-talk noise.
- What are the different ways to fix setup and hold? Which one is difficult to fix setup? or hold?
- Which violation you will fix first? Is it set up or hold?
- Tell me about scan-chain reordering.
- What are the timing arcs for flipflop when we have scan-chain reordering?
- How will you improve your insertion delay?
- And some other timing-related scenarios w.r.t. setup and hold fixes.
- Explain sanity checks.
- What check_design will report?
- What is the issue, if inputs are floating?
- Is there any issue in the case of outputs floating?
- What check_timing will report?
- What check_library will report?
- On what basis, macros will be keeping inside the design?
- What is the use of keep-out margin around the macros?
- Is it compulsory to keep out margin around macros?
- Explain the order of keeping preplace cells?
- Tap cells information will be in which file?
- On what basis, the distance between tap cells will be decided?
- Format of keeping tap cells inside the core area.
- How many std cells are being accommodated by each tap cell.
- What is the use of keeping tap cells in checkerboard format rather than keeping continuous?
- What is the purpose of endcap cells?
- Why can’t we keep endcaps on the top and bottom of macros?
- What is isolation cell, retentions cell?
- What are the checks after the floorplan?
- How the tool will place std cells in the design.
- How to fix congestion?
- Prioritize timing DRCs, timing, DRC.
- What is the purpose of IO buffers?
- Among Max Trans, Max cap, Max fanout.....which one will be fixed first.
- Difference between normal buffers and clock buffers.
- Checks after placement.
- What are the contents of the clock spec file?
- What is NDR?
- When we will enable NDR.
- What are the inputs to PT?
