for example if I 'deposite' a Q of a flip flop to a '0', it will remain a '0', untill the simulation updates it to a new value. It is like giving a initial value to a signal.
force ：不能将某个信号force成某个变量值；
//与SV中force语句相对应import "DPI-C" context function int uvm_hdl_force(string path,uvm_hdl_data_t value)//与SV中release语句相对应import "DPI-C" context function int uvm_hdl_release(string path)//与SV中assign语句相对应import "DPI-C" context function int uvm_hdl_deposit(string path,uvm_hdl_data_t value)//用于检查HDL path是否存在import "DPI-C" context function int uvm_hdl_check_path(string path)//用于读取HDL path变量的值import "DPI-C" context function int uvm_hdl_read(string path,output uvm_hdl_data_t value)//用于release然后读取HDL path变量的值import "DPI-C" context function int uvm_hdl_release_and_read(string path,inout uvm_hdl_data_t value)
force top.DUT.A = 0; //不可行uvm_hdl_force("top.DUT.A",0); //可行
下面是一个例子：
module rtla();wire [7:0] sig_a;endmodulemodule tb_top();rtla dut();endmodulemodule test();import uvm_pkg::*;`include "uvm_macros.svh"int read_value;initial beginforce tb_top.dut.sig_a = 8'h5a;`uvm_info("TEST",$sformatf("after normal force sig_a value is %b",tb_top.dut.sig_a),UVM_NONE)release tb_top.dut.sig_a;if(uvm_hdl_check_path("tb_top.dut.sig_a"))begin`uvm_info("TEST",$sformatf("uvm_hdl_check_path success, mean HDL path %s exists!","tb_top.dut.sig_a"),UVM_NONE)endif(uvm_hdl_deposit("tb_top.dut.sig_a",8'ha3))begin`uvm_info("TEST",$sformatf("after uvm deposit, sig_a value is %h",tb_top.dut.sig_a),UVM_NONE)endif(uvm_hdl_force("tb_top.dut.sig_a",8'h5c))begin`uvm_info("TEST",$sformatf("after uvm force, sig_a value is %h",tb_top.dut.sig_a),UVM_NONE)endif(uvm_hdl_read("tb_top.dut.sig_a",read_value))begin`uvm_info("TEST",$sformatf("after uvm force, read_value is %h",read_value),UVM_NONE)end//if(uvm_hdl_release("tb_top.dut.sig_a",read_value))begin //wrong codeif(uvm_hdl_release("tb_top.dut.sig_a"))begin`uvm_info("TEST",$sformatf("uvm release success"),UVM_NONE)endif(uvm_hdl_read("tb_top.dut.sig_a",read_value))begin`uvm_info("TEST",$sformatf("after uvm release, read_value is %h",read_value),UVM_NONE)endif(uvm_hdl_force("tb_top.dut.sig_a",8'haa))begin`uvm_info("TEST",$sformatf("after uvm force, sig_a value is %h",tb_top.dut.sig_a),UVM_NONE)endif(uvm_hdl_release_and_read("tb_top.dut.sig_a",read_value))begin`uvm_info("TEST",$sformatf("after uvm release, read_value is %h",read_value),UVM_NONE)endendendmodule
1、对于wire来说，release之后值将会立刻被改变为当前其他连线的驱动值。
2、其他类型则是release之后将会保持之前force的值直到下一次被assign新的值。
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