长刃在手枪出如龙 —— 探索Verilog-AXI开源库

import itertoolsimport loggingimport osimport random
import cocotb_test.simulatorimport pytest
import cocotbfrom cocotb.clock import Clockfrom cocotb.triggers import RisingEdge, Timerfrom cocotb.regression import TestFactory
from cocotbext.axi import AxiBus, AxiMaster, AxiRam

class TB(object):    def __init__(self, dut):        self.dut = dut
        self.log = logging.getLogger("cocotb.tb")        self.log.setLevel(logging.DEBUG)
        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
        self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)        self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)...

// Language: Verilog 2001
`resetall`timescale 1ns / 1ps`default_nettype none

module axi_cdma #(    // Width of data bus in bits    parameter AXI_DATA_WIDTH = 32,    // Width of address bus in bits    parameter AXI_ADDR_WIDTH = 16,    // Width of wstrb (width of data bus in words)    parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),    // Width of AXI ID signal    parameter AXI_ID_WIDTH = 8,    // Maximum AXI burst length to generate    parameter AXI_MAX_BURST_LEN = 16,    // Width of length field    parameter LEN_WIDTH = 20,    // Width of tag field    parameter TAG_WIDTH = 8,    // Enable support for unaligned transfers    parameter ENABLE_UNALIGNED = 0)

(    input  wire                       clk,    input  wire                       rst,
    /*     * AXI descriptor input     */    input  wire [AXI_ADDR_WIDTH-1:0]  s_axis_desc_read_addr,    input  wire [AXI_ADDR_WIDTH-1:0]  s_axis_desc_write_addr,    input  wire [LEN_WIDTH-1:0]       s_axis_desc_len,    input  wire [TAG_WIDTH-1:0]       s_axis_desc_tag,    input  wire                       s_axis_desc_valid,    output wire                       s_axis_desc_ready,
    /*     * AXI descriptor status output     */    output wire [TAG_WIDTH-1:0]       m_axis_desc_status_tag,    output wire [3:0]                 m_axis_desc_status_error,    output wire                       m_axis_desc_status_valid,

localparam [1:0]    AXI_RESP_OKAY = 2'b00,    AXI_RESP_EXOKAY = 2'b01,    AXI_RESP_SLVERR = 2'b10,    AXI_RESP_DECERR = 2'b11;
localparam [3:0]    DMA_ERROR_NONE = 4'd0,    DMA_ERROR_TIMEOUT = 4'd1,    DMA_ERROR_PARITY = 4'd2,    DMA_ERROR_AXI_RD_SLVERR = 4'd4,

module axi_cdma #...-input--output--parameter--localparam--reg--wire--assign--always-

always @* begin    state_next = STATE_IDLE;
    id_next = id_reg;    addr_next = addr_reg;    data_next = data_reg;    resp_next = resp_reg;    ruser_next = ruser_reg;    burst_next = burst_reg;    burst_size_next = burst_size_reg;    master_burst_next = master_burst_reg;    master_burst_size_next = master_burst_size_reg;
    s_axi_arready_next = 1'b0;    m_axi_arid_next = m_axi_arid_reg;    m_axi_araddr_next = m_axi_araddr_reg;    m_axi_arlen_next = m_axi_arlen_reg;    m_axi_arsize_next = m_axi_arsize_reg;    m_axi_arburst_next = m_axi_arburst_reg;    m_axi_arlock_next = m_axi_arlock_reg;    m_axi_arcache_next = m_axi_arcache_reg;    m_axi_arprot_next = m_axi_arprot_reg;    m_axi_arqos_next = m_axi_arqos_reg;    m_axi_arregion_next = m_axi_arregion_reg;    m_axi_aruser_next = m_axi_aruser_reg;    m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_arready;    m_axi_rready_next = 1'b0;
    if (SEGMENT_COUNT == 1) begin        // master output is same width; direct transfer with no splitting/merging        s_axi_rid_int = id_reg;        s_axi_rdata_int = m_axi_rdata;        s_axi_rresp_int = m_axi_rresp;        s_axi_rlast_int = m_axi_rlast;        s_axi_ruser_int = m_axi_ruser;        s_axi_rvalid_int = 0;
        case (state_reg)            STATE_IDLE: begin                // idle state; wait for new burst                s_axi_arready_next = !m_axi_arvalid;
                if (s_axi_arready && s_axi_arvalid) begin                    s_axi_arready_next = 1'b0;                    id_next = s_axi_arid;                    m_axi_arid_next = s_axi_arid;                    m_axi_araddr_next = s_axi_araddr;                    m_axi_arlen_next = s_axi_arlen;                    m_axi_arsize_next = s_axi_arsize;                    m_axi_arburst_next = s_axi_arburst;                    m_axi_arlock_next = s_axi_arlock;                    m_axi_arcache_next = s_axi_arcache;                    m_axi_arprot_next = s_axi_arprot;                    m_axi_arqos_next = s_axi_arqos;                    m_axi_arregion_next = s_axi_arregion;

always @(posedge clk) begin    rd_ptr_reg <= rd_ptr_next;    rd_addr_reg <= rd_ptr_next;
    mem_read_data_valid_reg <= mem_read_data_valid_next;
    if (read) begin        mem_read_data_reg <= mem[rd_addr_reg[FIFO_ADDR_WIDTH-1:0]];    end
    if (rst) begin        rd_ptr_reg <= {FIFO_ADDR_WIDTH+1{1'b0}};        mem_read_data_valid_reg <= 1'b0;    endend