今日为大家播报🔔
英国Apple已开放2024全职
想投递的同学们take the chance！
Minimum of BSc in EE.
Experience with physical synthesis, including logic and PPA optimisation techniques.
Understanding and application of physical design and static timing analysis principles.
Proficient in Verilog and/or System Verilog and scripting languages.
- 关岗时间：招满即止，尽快申请
