IIC总线介绍及FPGA编程（七）：FPGA代码通读【完结】

文摘科技 2024-03-10 23:02 天津

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今天为“IIC总线介绍及FPGA编程”的第七章“FPGA代码通读"讲解。

视频中文字内容：

之后我们通读一遍程序代码lb2iic_module.vhd：

建立最顶层，树形结构是这样的：

顶层程序的写法：单字节写测试程序：

  process(I_rst, S_clk_40M)  begin    if I_rst = '0' then      S_cs_n <= '1';      S_wr_n <= '1';      S_rd_n <= '1';      ST_wr <= M_idle;    elsif S_clk_40M'event and S_clk_40M = '1' then      S_busy_bufs(0) <= S_busy;      S_busy_bufs(1) <= S_busy_bufs(0);      --单字节写      case ST_wr is        when M_idle =>          if I_key_start = '0' then            ST_wr <= M_wr;            end if;        when M_wr =>          S_cs_n <= '0';          S_wr_n <= '0';          S_addr <= x"15";          S_data_in <= x"5a";          S_byte_num <= 1;          if S_abyte = '1' then            S_cs_n <= '1';            S_wr_n <= '1';                      end if;        when others =>          ST_wr <= M_idle;      end case;    end if;  end process;

连续写：测试程序：

  process(I_rst, S_clk_40M)  begin    if I_rst = '0' then      S_cs_n <= '1';      S_wr_n <= '1';      S_rd_n <= '1';      ST_wr <= M_idle;    elsif S_clk_40M'event and S_clk_40M = '1' then      S_busy_bufs(0) <= S_busy;      S_busy_bufs(1) <= S_busy_bufs(0);      --连续写      case ST_wr is        when M_idle =>          if I_key_start = '0' then            S_cs_n <= '0';            S_wr_n <= '0';            S_addr <= x"15";            S_data_in <= x"5a";            S_byte_num <= 8;            ST_wr <= M_wr;            end if;        when M_wr =>          if S_abyte = '1' then            S_data_in <= S_data_in + '1';                      end if;          if S_busy_bufs(1) = '1' and S_busy_bufs(0) = '0' then            S_cs_n <= '1';            S_wr_n <= '1';                      end if;        when others =>          ST_wr <= M_idle;      end case;    end if;  end process;

单字节读测试程序：

  process(I_rst, S_clk_40M)  begin    if I_rst = '0' then      S_cs_n <= '1';      S_wr_n <= '1';      S_rd_n <= '1';      ST_wr <= M_idle;    elsif S_clk_40M'event and S_clk_40M = '1' then      S_busy_bufs(0) <= S_busy;      S_busy_bufs(1) <= S_busy_bufs(0);      --单字节读      case ST_wr is        when M_idle =>          if I_key_start = '0' then            S_cs_n <= '0';            S_rd_n <= '0';            S_addr <= x"15";            S_byte_num <= 1;            ST_wr <= M_wr;            end if;        when M_wr =>          if S_busy_bufs(1) = '1' and S_busy_bufs(0) = '0' then            S_cs_n <= '1';            S_rd_n <= '1';              S_data_reg <= S_data_out;                  end if;        when others =>          ST_wr <= M_idle;      end case;    end if;  end process;

连续读测试程序：

  process(I_rst, S_clk_40M)  begin    if I_rst = '0' then      S_cs_n <= '1';      S_wr_n <= '1';      S_rd_n <= '1';      ST_wr <= M_idle;    elsif S_clk_40M'event and S_clk_40M = '1' then      S_busy_bufs(0) <= S_busy;      S_busy_bufs(1) <= S_busy_bufs(0);      --连续读      case ST_wr is        when M_idle =>          if I_key_start = '0' then            S_cs_n <= '0';            S_rd_n <= '0';            S_addr <= x"15";            S_byte_num <= 8;            ST_wr <= M_wr;            end if;        when M_wr =>          if S_abyte = '1' then            S_data_reg <= S_data_out;                      end if;          if S_busy_bufs(1) = '1' and S_busy_bufs(0) = '0' then            S_cs_n <= '1';            S_rd_n <= '1';                  end if;        when others =>          ST_wr <= M_idle;      end case;    end if;  end process;

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