博文速递：Introduction and Source of Clock Skew

It's very important to understand the Skew and how it impact the timing analysis. Few different flavor of Definition. :)

 ·It's a difference between the clock arrival time across the chip.

 ·It's the time delta between the actual and expected arrival time of a clock signal.

 ·Clock skew is the timing differences between signals in a clock distribution system

 ·Variation of arrival of clock at destination points in the clock Network.

As you can see in this pic, positive edge of both the clock signal (CLK1 and CLK2) has some time delay even when there is Same clock source (CLK_S). This Time delay is known as CLOCK SKEW.

There are lot of thinks which I was trying to write down here but later I decide to record that part. 

Source of Clock Skew

In general Clock skew has 2 Distant sources.

1.Clock Driver or Clock Buffer

2.Clock Distribution System

Clock Driver and Clock Buffer:

Clock Buffer is a special type of Buffer which is required to keep the Transition with in a certain range. We will discuss this in detail in terms of Layout and all but important thing these are designed specially for Clock path. Ideally all the clock buffer / clock driver, all the internal circuit elements should matched perfectly so that the propagation delays become identical. In a practical clock driver there are many variables which can effect the propagation delay when though paths are equivalent and these effects /parameters contribute to skew. Few of them are:

·The layout and electrical characteristics of the gate components

  -Output Load Vs Current characteristic

  -Input Transition Vs Delay Characteristic

  -Different Resistance of Internal VIA and Metal wire

·The location of those components relative to ground and VCC

  -Different Capacitance which can effect Charging and discharging time

  -Internal Coupling Cap difference

·In Die Process, Voltage, Temperature (PVT) variation

  -Different clock buffers with different channel lengths

  -Local drop in voltage leads to increased buffer delay

  -Device mismatch across die

  -Hot spots lead to increased gate delay

Clock Distribution System:

This is second source of clock skew which is playing a significant role in lower nodes. The Clock buffer is important in clock distribution but how that distribution is done is very important. If it's uneven, then you will notice a skew between 2 Clock. Practically what ever you do, you can't design 2 wires with all environment identical. And because of this difference you will see a difference in Net delay, which contribute in SKEW. Few source of difference are:

·Wire Coupling

  -Coupling will be different on different clock routes.

  -Near by Signal Lines can distort (add delay) the Clock signal because of coupling effect.

  -Nearby Power Line can also effect the Wire coupling.

·RC Mismatch

  -Clock routes not all of equal length.

  -Latches or Flip Flop not all equal distance from Clock buffer.

  -Device Loading

·Process, Voltage, Temperature (PVT) variation

  -Hot spots lead to increased wire delay.

  -Manufacturing Effects can change the width/thickness of wire, which result different delay.

·Unequal Buffering

  -Unequal buffering can cause additional skew due to rise time/fall time dependent delay in buffers.

  -Change the Load of previous Stage.

  -Contribute in different transition time means different wire delay.

In summary, I can say that if you need to understand the Sources of Skew, you need to understand how many type of delays are there ? How delay changes with respect to different parameters like output load, Input transition, Temperature and all.

You can refer few of my previous articles which can give you some direction to think. I will see later, if there is any need to add more content.